כניסההרשמה
חזרה

Verification Engineer

abra
שכר לא צויןCenter, Center, Israel, מהמשרדמידמשרה מלאה
משרה חיצונית, ההגשה באתר החברהאושר שהמשרה פתוחה לפני 9 שעות

abra R&D is looking for a Verification Engineer to develop UVM-based verification environments for FPGA projects involving signal processing, controllers, and other technologies. The role includes RTL debugging and close collaboration with FPGA development, system, architecture, and algorithm teams.

מה תעשו

  • Develop UVM verification environments for FPGA projects.
  • Define, architect, and develop verification environments from block level to full-chip level.
  • Support RTL debugging from block level to system level.
  • Work with FPGA development, system, architecture, and algorithm teams.
  • Verify projects involving signal processing, controllers, and other technologies.

דרישות

  • 3+ years of verification experience, from test plan definition through coverage.
  • Hands-on experience with UVM and SystemVerilog.
  • Experience developing FPGA / ASIC verification environments at block and full-chip levels.
  • Experience with RTL debugging from block level to system level.
  • Experience writing scripts in Python, TCL, Bash, or Csh, and working in a Linux environment.
  • Very good technical English.

יתרון

  • B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science.
  • Experience with Questa Simulator.

תנאי סף

  • 3+ years of verification experience, from test plan definition through coverage
  • Hands-on experience with UVM and SystemVerilog
  • Experience developing FPGA / ASIC verification environments at block and full-chip levels
  • Experience with RTL debugging from block level to system level
UVMSystemVerilogFPGA VerificationASIC VerificationRTL debuggingPythonTCLLinux